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Gate Matrix Layout

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3 Author(s)
Wing, O. ; Department of Electrical Engineering, Columbia University, New York, NY, USA ; Shuo Huang ; Rui Wang

A graph-theoretic description of the problem of layout of CMOS circuits in the style of gate matrix in minimum area is presented. The problem is formulated as one of finding two assignment functions f and h such that the layout L(f, h) requires the minimum number of rows of the gate matrix. The function f maps the distinct gates of the transistors to the columns of the gate matrix and the function h maps the nets of the circuit to the rows such that all of the vertical diffusion runs which connect nets on different rows are realizable. A two-stage approach to the problem is described which first obtains a layout without regard to the vertical constraints and then rows are permuted to satisfy the constraints. Detailed algorithms and examples are given. The gate matrix layout of a 118-transistor circuit was obtained in 9 s on a mainframe computer.

Published in:

Computer-Aided Design of Integrated Circuits and Systems, IEEE Transactions on  (Volume:4 ,  Issue: 3 )