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Tolerance Assignment for IC Selection Tests

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2 Author(s)
Maly, W. ; Department of Electrical and Computer Engineering, Carnegie-Mellon University, Pittsburgh, PA, USA ; Pizlo, Z.

IC chips or manufactured wafers run through selection processes at various stages of the fabrication process. Typically, the most important is the selection performed on IC dice which are tested directly on manufacturing wafers. This paper deals with the problem of the optimal assignment of the upper and lower selection thresholds applied for selecting dice during the wafer measurements. The tolerance assignment is defined as a statistical optimization problem, where the optimization objective function is a measure of the manufacturing profit. In the paper a method for computing a solution of this optimization problem is proposed, and an example of the industrial application of this method in the Computer-Aided Manufacturing (CAM) area is given.

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Computer-Aided Design of Integrated Circuits and Systems, IEEE Transactions on  (Volume:4 ,  Issue: 2 )