By Topic

A Pattern Recognition Based Method for IC Failure Analysis

Sign In

Cookies must be enabled to login.After enabling cookies , please use refresh or reload or ctrl+f5 on the browser for the login options.

Formats Non-Member Member
$31 $13
Learn how you can qualify for the best price for this item!
Become an IEEE Member or Subscribe to
IEEE Xplore for exclusive pricing!
close button

puzzle piece

IEEE membership options for an individual and IEEE Xplore subscriptions for an organization offer the most affordable access to essential journal articles, conference papers, standards, eBooks, and eLearning courses.

Learn more about:

IEEE membership

IEEE Xplore subscriptions

2 Author(s)
Strojwas, A.J. ; Carnegie-Mellon University, Pittsburgh, PA, USA ; Director, S.W.

Random fluctuations which are inherent in the IC manufacturing process cause production yields to be significantly less than 100 percent. Yield drop is caused by two types of faults, catastrophic and parametric. This paper deals with the diagnosis of parametric faults which occur during the manufacturing of IC's and cause the yield to drop below some acceptable level. A statistical pattern recognition approach to IC failure analysis is developed in this paper. Identification of faults is based on the analysis of the joint probability density function of circuit performances. A number of alternative approaches to IC failure analysis are developed and their efficiency is discussed. Also a complete statistical pattern recognition system with learning capability is proposed and all the stages of its development are discussed. An efficient method for fault simulation which is based upon statistical process simulation is proposed. The performance of the algorithms proposed in this paper has been successfully verified for data collected from commercial fabrication processes and from computer simulation.

Published in:

Computer-Aided Design of Integrated Circuits and Systems, IEEE Transactions on  (Volume:4 ,  Issue: 1 )