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CHAMP: Chip Floor Plan for Hierarchical VLSI Layout Design

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3 Author(s)
Ueda, K. ; Atsugi Electrical Communication Laboratory, N.T.T., Atsugi, Kanagawa, Japan. ; Kitazawa, H. ; Harada, I.

In a hierarchical VLSI layout design, the block-level layout design is called a "chip floor plan." In this paper, a semi-automatic VLSI chip floor plan algorithm and its implementation are presented. The initial block placement is obtained by an attractive and repulsive force method (AR method), and the subsequent block packing process is performed by gradually moving and reshaping blocks with chip boundary shrinking. The chip area estimation is performed by using individual block area calculations from empirically obtained equations. A set of interactive commands is also provided to facilitate the manual optimization processes using a color graphic terminal. By processing several practical VLSI circuits, it is shown that the method is very effective for handling various kinds of blocks and is able to reduce the design effort required to achieve the chip floor plan.

Published in:

Computer-Aided Design of Integrated Circuits and Systems, IEEE Transactions on  (Volume:4 ,  Issue: 1 )