By Topic

An Approach to Topological Pin Assignment

Sign In

Cookies must be enabled to login.After enabling cookies , please use refresh or reload or ctrl+f5 on the browser for the login options.

Formats Non-Member Member
$31 $13
Learn how you can qualify for the best price for this item!
Become an IEEE Member or Subscribe to
IEEE Xplore for exclusive pricing!
close button

puzzle piece

IEEE membership options for an individual and IEEE Xplore subscriptions for an organization offer the most affordable access to essential journal articles, conference papers, standards, eBooks, and eLearning courses.

Learn more about:

IEEE membership

IEEE Xplore subscriptions

1 Author(s)
Brady, H.N. ; V. R. Information Systems, Inc., Austin, TX, USA

One of the methods of increasing routability of an integrated circuit or printed circuit board, is to improve the assignment of connection nets to component (gate, chip, etc.) pins. The quality of a pin assignment is judged based on factors such as predicted wire length, wiring crossovers, and wiring congestion. This paper describes topological heuristic algorithms for pin assignment. Two stages, initial pin assignment and assignment improvement, are described in detail. For all cases, example diagrams are provided. The heuristic approaches demonstrated are highly tunable to specific routers.

Published in:

Computer-Aided Design of Integrated Circuits and Systems, IEEE Transactions on  (Volume:3 ,  Issue: 3 )