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Fault Modeling for Digital MOS Integrated Circuits

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1 Author(s)
Hayes, J.P. ; Department of Electrical Engineering and Computer Science, University of Michigan, Ann Arbor, MI, USA

A new fault modeling technique aimed at efficient simulation and test generation for complex digital MOS IC's is described. It is based on connector-switch-attenuator (CSA) analysis, which employs purely digital models of switching transistors, resistive/capacitive elements, and their associated signals. The use of CSA networks to model the digital behavior, both static and dynamic, of MOS circuits is reviewed. It is shown that most physical failure modes in such circuits, including short-circuit, open-circuit, and delay faults, can be modeled more efficiently by CSA models than by conventional approaches. A generalized single stuck-line (GSSL) fault model is suggested as a uniform and practical method for fault representation.

Published in:

Computer-Aided Design of Integrated Circuits and Systems, IEEE Transactions on  (Volume:3 ,  Issue: 3 )