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A Hierarchical Standard Cell Approach for Custom VLSI Design

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6 Author(s)
Tokuda, T. ; LSI Research Laboratory, Mitsubishi Electric Corporation, Itami, Japan ; Korematsu, J. ; Tomisawa, O. ; Asai, S.
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A custom VLSI design technique, using an integrated CAD system is described. The design system features on the hierarchical design process and layout design capability by system designers (customers). As for application, high-performance LSI's for 16-bit CPU were developed. The LSI design was accomplished in a short period (three months with three designers) due to the hierarchical standard cell approach. The LSI chip contains about 20 K transistors in an 8.84 mm X 8.88 mm die area. High-speed operation (machine cycle = 200 ns) and a high density of 291 transistors/mm2 were obtained with low power consumption (1.2 W) owing to the mixed-MOS type standard cell library and this approach.

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Computer-Aided Design of Integrated Circuits and Systems, IEEE Transactions on  (Volume:3 ,  Issue: 3 )