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A global router for gate array LSI's is described, which is intended to perform an interaction between placement and routing such that the features of one may be incorporated into those of another. This router is to generate for each net an interconnection pattern of channel segments in such a unified way of taking all interrelated interconnection requirements into account at once. A main objective of the router is not only to minimize the maximum of the local routing densities but also to distribute all the wiring requirements over channels evenly, in order to attain 100-percent interconnections within a limited area. An implementation result of the router is also shown.