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Single-Layer Routing for VLSI: Analysis and Algorithms

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2 Author(s)
Marek-Sadowska, M. ; Department of Electrical Engineering and Computer Sciences and the Electronics Research Laboratory, University of California, Berkeley, CA, USA ; Tom Tsan-Kuo Tarng

In this paper we present a discussion of planarity testing and detailed single-layer routing. A program which implements the proposed algorithms for routing nets inside an arbitrarily shaped region has been written and tested. The results from this program are shown as examples.

Published in:

Computer-Aided Design of Integrated Circuits and Systems, IEEE Transactions on  (Volume:2 ,  Issue: 4 )

Date of Publication:

October 1983

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