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Programmable logic arrays are important building blocks of VLSI circuits and systems. We address the problem of optimizing the silicon area and the performances of large logic arrays. In particular, we describe a general method for compacting a logic array defined as multiple row and column folding and we address the problem of interconnecting a PLA to the outside circuitry. We define a constrained optimization problem to achieve minimal silicon area occupation with constrained positions of electrical inputs and outputs. We present a new computer program, PLEASURE, which implements several algorithms for multiple and/or constrained PLA folding.