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Resistance Extraction from Mask Layout Data

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2 Author(s)
M. Horowitz ; Department of Electrical Engineering, Stanford University, Palo Alto, CA, USA ; R. W. Dutton

This paper presents a new algorithm to extract resistance values from an integrated circuit artwork description. Instead of trying to solve for the exact resistance values, heuristics are used to find an approximate solution. The algorithm first breaks the input polygons into simple pieces, and then finds the resistance through each piece. This procedure enables the extraction to be both fast and memory efficient. The heuristics used for splitting the polygons and calculating the pieces' resistance are derived from rules of electrostatics, and yield answers that are within 10 percent of the exact resistance values. The operations needed to break complex polygons into simpler pieces are very similar to other geometric operations used in artwork analysis systems.

Published in:

IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems  (Volume:2 ,  Issue: 3 )