Skip to Main Content
This paper focuses on automatic synthesis of digital hardware from a behavioral description. Algorithms have been written and tested to perform automatic generation of control hardware and optimized microcode for specified data paths. The optimization algorithms produce a family of results based on cost and speed constraints supplied by the user. The algorithms adapt to these constraints and adjust the amount of parallelism in the synthesized microcode accordingly. Tests were run by generating microcode for a PDP-11/40. Results compared favorably with the human design.