Skip to Main Content
The phase-locked loop (PLL) is one of the key building blocks of modern electronic designs. This paper presents a novel PLL structure that utilizes a "flying-adder" frequency synthesizer as its digital control oscillator (DCO), a software implemented adaptive IIR filter as its loop filter, and a unique counter as its phase detector. This all-digital PLL (ADPLL) achieved the desired functionality with additional advantages including no off-chip R and C components required, dynamic control of the loop gain on the fly, easy implementation on the digital CMOS process. This paper presents detailed descriptions of each component of this ADPLL; it also presents the system modeling in Z-domain, by mapping from S-domain, for dynamic response, stability, and steady-state error study.