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A 500-MHz-1.25-GHz fast-locking pulsewidth control loop with presettable duty cycle

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2 Author(s)
Sung-Rung Han ; Dept. of Electr. Eng., Nat. Taiwan Univ., Taipei, Taiwan ; Shen-Iuan Liu

A 500-MHz-1.25-GHz fast-locking pulsewidth control loop (PWCL) with presettable duty cycle is realized in 0.35-μm CMOS technology. The proposed voltage-difference-to-digital converter and switched charge pump circuits reduce the lock time of a conventional PWCL. Compared with the conventional PWCL, the proposed circuit can reduce the lock time by a factor of 2.58. A method to preset the duty cycle of the output clock is also described. Circuit measurements verify that the duty cycle of the output clock can be adjusted from 35% to 70% in steps of 5%.

Published in:

Solid-State Circuits, IEEE Journal of  (Volume:39 ,  Issue: 3 )