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Synthesis of fully testable circuits from BDDs

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3 Author(s)
R. Drechsler ; Inst. of Comput. Sci., Univ. of Bremen, Germany ; Junhao Shi ; G. Fey

We present a technique to derive fully testable circuits under the stuck-at fault model (SAFM) and the path-delay fault model (PDFM). Starting from a function description as a binary decision diagram, the netlist is generated by a linear time mapping algorithm. Only one additional input and one inverter are needed to achieve 100% testable circuits under SAFM and PDFM. Experiments are given to show the advantages of the technique.

Published in:

IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems  (Volume:23 ,  Issue: 3 )