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X-compact: an efficient response compaction technique

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2 Author(s)
S. Mitra ; Intel Corp., Sacramento, CA, USA ; Kee Sup Kim

X-Compact is an X-tolerant test response compaction technique. It enables up to exponential reduction in the test response data volume and the number of pins required to collect test response from a chip. The compaction hardware requires negligible area, does not add any extra delay during normal operation, guarantees detection of defective chips even in the presence of unknown logic values (often referred to as X's), and preserves diagnosis capabilities for most practical scenarios. The technique has minimum impact on current design and test flows, and can be used to reduce test time, test-data volume, test-input/output pins and tester channels, and also to improve test quality.

Published in:

IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems  (Volume:23 ,  Issue: 3 )