By Topic

Scaled 2bit/cell SONOS type nonvolatile memory technology for sub-90nm embedded application using SiN sidewall trapping structure

Sign In

Cookies must be enabled to login.After enabling cookies , please use refresh or reload or ctrl+f5 on the browser for the login options.

Formats Non-Member Member
$31 $13
Learn how you can qualify for the best price for this item!
Become an IEEE Member or Subscribe to
IEEE Xplore for exclusive pricing!
close button

puzzle piece

IEEE membership options for an individual and IEEE Xplore subscriptions for an organization offer the most affordable access to essential journal articles, conference papers, standards, eBooks, and eLearning courses.

Learn more about:

IEEE membership

IEEE Xplore subscriptions

3 Author(s)
Fukuda, M. ; Fujitsu Labs. Ltd., Kanagawa, Japan ; Nakanishi, T. ; Nara, Y.

We demonstrate and experimentally investigate the scalability of a new 2bit/cell SONOS type nonvolatile memory cell. This memory has single layer of gate oxide and SiN sidewalls at both sides of the gate to store the charge. We have found the sidewall trapping structure is much more scalable than conventional planar SONOS structures by the precise control of alignment between the pn junction edge and the SiN sidewall. The proposed device with gate length down to 60 nm was successfully operated with the Vth window, which is the Vth difference between forward and reverse operation, of 0.6 V. Also, by employing a 2D device simulator, we found that the degradation mechanism after cycled endurance testing is the negative charge accumulation near the SiO/sub 2//Si interface on the source/drain region.

Published in:

Electron Devices Meeting, 2003. IEDM '03 Technical Digest. IEEE International

Date of Conference:

8-10 Dec. 2003