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A computational study of ballistic silicon nanowire transistors

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3 Author(s)
J. Wang ; Purdue Univ., West Lafayette, IN, USA ; E. Polizzi ; M. Lundstrom

Using a rigorous 3D quantum simulator, we report a computational study of ballistic silicon nanowire transistors with arbitrary cross sections (i.e., triangular, rectangular or cylindrical). In comparison with the planar double-gate MOSFET, the silicon nanowire transistor shows promise (e.g., better electrostatic scaling for a given Si body thickness) and may provide a manufacturable opportunity to scale silicon transistors down below the scaling limit of planar MOSFETs.

Published in:

Electron Devices Meeting, 2003. IEDM '03 Technical Digest. IEEE International

Date of Conference:

8-10 Dec. 2003