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A robust 65-nm node CMOS technology for wide-range Vdd operation

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20 Author(s)
Nakahara, Y. ; Adv. Technol. Dev. Div., NEC Electron. Corp., Kanagawa, Japan ; Fukai, T. ; Togo, M. ; Koyama, S.
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We have developed a highly reliable 65 nm node CMOS technology, enabling a wide-range of Vdd operation, including overdrive mode. Process conditions are carefully optimized from the various aspects of device reliability and performance. We have utilized an oxynitride gate, arsenic-assisted phosphorus S/D ion-implantation, Ni-silicidation, stress controlled SiN layer process, and an offset-spacer process in order to improve the drive-current at low voltage operation and reliability at high voltage operation. The obtained drive-currents are 730/310 /spl mu/A//spl mu/m with an off-current of 80 nA//spl mu/m at a standard supply voltage of 0.9 V, and 1150/550 /spl mu/A//spl mu/m with an off-current of 180 nA//spl mu/m at an overdrive voltage of 1.2 V, while satisfying strict criteria for transistor reliability.

Published in:

Electron Devices Meeting, 2003. IEDM '03 Technical Digest. IEEE International

Date of Conference:

8-10 Dec. 2003