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High speed 45nm gate length CMOSFETs integrated into a 90nm bulk technology incorporating strain engineering

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19 Author(s)
Chan, V. ; Dev. Center, IBM Semicond. Res., Hopewell Junction, NY, USA ; Rengarajan, R. ; Rovedo, N. ; Wei Jin
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A leading edge 90 nm logic bulk foundry technology with 45 nm gate length devices, incorporating strain engineering, is described in this paper. Gate length and dielectric scaling, along with optimized strain engineering, enable high performance devices, which are amongst the best reported to date. Short channel effect control down to 35 nm is demonstrated. Both NMOS and PMOS performance are improved through careful optimization of stress effects from both trench isolation and contact etch stop nitride film. Furthermore, analysis of the channel mobility and current enhancement is used to gain understanding of the stress mechanisms, and hence layout design practice should be optimized for performance.

Published in:

Electron Devices Meeting, 2003. IEDM '03 Technical Digest. IEEE International

Date of Conference:

8-10 Dec. 2003