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Static noise margin of the full DG-CMOS SRAM cell using bulk FinFETs (Omega MOSFETs)

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18 Author(s)
Park, T. ; Semicond. R&D Center, Samsung Electron. Co. Ltd., Kiheung, South Korea ; Cho, H.J. ; Choe, J.D. ; Han, S.Y.
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The operational six-transistor SRAM cell was experimentally demonstrated using bulk FinFET CMOS technology. A cell size of 0.79 /spl mu/m/sup 2/ was achieved by 90 nm node technology, with stable operation at 1.2 V using 4 levels of W and Al interconnects. Static noise margin of 280 mV was obtained at V/sub cc/ of 1.2 V. To our knowledge, this represents the first experimental demonstration of a fully integrated bulk FinFET SRAM cell.

Published in:

Electron Devices Meeting, 2003. IEDM '03 Technical Digest. IEEE International

Date of Conference:

8-10 Dec. 2003

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