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Energy-efficient design for highly associative instruction caches in next-generation embedded processors

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4 Author(s)
Aragon JL ; Center for Embedded Comput. Syst., California Univ., Irvine, CA, USA ; Nicolaescu, D. ; Veidenbaum, A. ; Badulescu, A.-M.

This paper proposes a low-energy solution for CAM-based highly associative I-caches using a segmented word-line and a predictor-based instruction fetch mechanism. Not all instructions in a given I-cache fetch are used due to branches. The proposed predictor determines which instructions in a cache access will be used and does not fetch any other instructions. Results show an average I-cache energy savings of 44% over the baseline case and 6% over the segmented case with no negative impact on performance.

Published in:

Design, Automation and Test in Europe Conference and Exhibition, 2004. Proceedings  (Volume:2 )

Date of Conference:

16-20 Feb. 2004