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Memmap: technology mapping algorithm for area reduction in FPGAs with embedded memory arrays using reconvergence analysis

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3 Author(s)
A. Manoj Kumar ; Indian Inst. of Technol., Madras, India ; J. Bobba ; V. Kamakoti

Modern day field programmable gate arrays (FPGA) include in addition to look-up tables, reasonably big configurable embedded memory blocks (EMB) to cater to the on-chip memory requirements of systems/applications mapped on them. While mapping applications on to such FPGAs, some of the EMBs may be left unused. This paper presents a methodology to utilize such unused EMBs as large look-up tables to map multi-output combinational sub-circuits of the application, which, otherwise would be mapped on to a number of small look-up tables (LUT) available on the FPGA. This in turn leads to a huge reduction in the area of the FPGA, utilized for mapping an application. Experimental results show that our proposed methodology, when employed on popular benchmark circuits, can lead to additional 50% reduction in area utilized when compared with other methodologies reported in the literature.

Published in:

Design, Automation and Test in Europe Conference and Exhibition, 2004. Proceedings  (Volume:2 )

Date of Conference:

16-20 Feb. 2004