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A mapping strategy for resource-efficient network processing on multiprocessor SoCs

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4 Author(s)
Grunewald, M. ; Dept. of Electr. Eng., Paderborn Univ., Germany ; Niemann, J.-C. ; Porrmann, M. ; Ruckert, U.

Hardware architectures based on a field of hardware-extended processors can provide flexible computing power for applications where parallelism can be exploited. For multiprocessors, the assignment of functionality to execution units can have a great impact on the performance. Additionally, finding the optimal mapping can be a time-consuming task. We present a multiprocessor architecture along with a suitable design method that includes an automated solution to the mapping problem. Our hardware architecture employs a network-on-chip (NoC) to achieve a high degree of scalability for the application and for the system in respect to future integration technologies. We also show how to reduce the packet buffer requirements with a proper scheduling strategy and present first estimates for the resource consumption of an application targeted for mobile networking.

Published in:

Design, Automation and Test in Europe Conference and Exhibition, 2004. Proceedings  (Volume:2 )

Date of Conference:

16-20 Feb. 2004