Referenced Items are not available for this document.
We present a sensitivity-based algorithm for total power including dynamic and subthreshold leakage power minimization using simultaneous sizing, Vdd and Vth assignment. The proposed algorithm is implemented and tested on a set of combinational benchmark circuits. A comparison with traditional CVS based algorithms demonstrates the advantage of the algorithm including an average power reduction of 37% at primary input activities of 0.1. We also investigate the impact of various low Vdd values on total power savings.
Published in:
Design, Automation and Test in Europe Conference and Exhibition, 2004. Proceedings
(Volume:1
)
Date of Conference: 16-20 Feb. 2004
- Page(s):
- 718 - 719 Vol.1
- ISSN :
- 1530-1591
- Print ISBN:
- 0-7695-2085-5
- INSPEC Accession Number:
- 7993198
- Digital Object Identifier :
- 10.1109/DATE.2004.1268946
- Product Type:
- Conference Publications
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