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Decomposition of instruction decoder for low power design

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3 Author(s)
Wu-An Kuo ; Dept. of Comput. Sci., Tsing Hua Univ., Hsin-Chu, Taiwan ; TingTing Hwang ; Wu, A.C.H.

Microprocessors have been used in wide-ranged applications. During the execution of instructions, instruction decoding is a major task for identifying instructions and generating control signals for data-paths. By exploiting program behaviors, we propose a novel instruction-decoding approach for power minimization. Using the proposed instruction-decoding structure, we present a partitioning method that decomposes the instruction-decoding circuit into two sub-circuits according to the execution frequencies of instructions. Using our proposed decoding structure, only one sub-circuit will be activated when executing an instruction. Experimental results have demonstrated that our proposed approach achieves on an average of 26.71% and 15.69% power reductions for the instruction decoder and the control unit, respectively.

Published in:

Design, Automation and Test in Europe Conference and Exhibition, 2004. Proceedings  (Volume:1 )

Date of Conference:

16-20 Feb. 2004