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System-level performance analysis in SystemC

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5 Author(s)
Posadas, H. ; Dept. of TEISA, Cantabria Univ., Santander, Spain ; Herrera, F. ; Sanchez, P. ; Villar, E.
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As both the ITRS and the Medea+ DA Roadmaps have highlighted, early performance estimation is an essential step in any SoC design methodology based on International Technology Roadmap for Semiconductors (2001) and The MEDEA+ Design Automation Roadmap (2002). This paper presents a C++ library for timing estimation at system level. The library is based on a general and systematic methodology that takes as input the original SystemC source code without any modification and provides the estimation parameters by simply including the library within a usual simulation. As a consequence, the same models of computation used during system design are preserved and all simulation conditions are maintained. The method exploits the advantages of dynamic analysis, that is, easy management of unpredictable data-dependent conditions and computational efficiency compared with other alternatives (ISS or RT simulation, without the need for SW generation and compilation and HW synthesis). Results obtained on several examples show the accuracy of the method. In addition to the fundamental parameters needed for system-level design exploration, the proposed methodology allows the designer to include capture points at any place in the code. The user can process the corresponding captured events for unrestricted timing constraint verification.

Published in:

Design, Automation and Test in Europe Conference and Exhibition, 2004. Proceedings  (Volume:1 )

Date of Conference:

16-20 Feb. 2004