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A logic level design methodology for a secure DPA resistant ASIC or FPGA implementation

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2 Author(s)
Tiri, K. ; Dept. of Electr. Eng., UCLA, Los Angeles, CA, USA ; Verbauwhede, I.

This paper describes a novel design methodology to implement a secure DPA resistant crypto processor. The methodology is suitable for integration in a common automated standard cell ASIC or FPGA design flow. The technique combines standard building blocks to make 'new' compound standard cells, which have a close to constant power consumption. Experimental results indicate a 50 times reduction in the power consumption fluctuations.

Published in:

Design, Automation and Test in Europe Conference and Exhibition, 2004. Proceedings  (Volume:1 )

Date of Conference:

16-20 Feb. 2004

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