By Topic

Exploiting the high-frequency performance of low-voltage low-power SC filters

Sign In

Cookies must be enabled to login.After enabling cookies , please use refresh or reload or ctrl+f5 on the browser for the login options.

Formats Non-Member Member
$33 $13
Learn how you can qualify for the best price for this item!
Become an IEEE Member or Subscribe to
IEEE Xplore for exclusive pricing!
close button

puzzle piece

IEEE membership options for an individual and IEEE Xplore subscriptions for an organization offer the most affordable access to essential journal articles, conference papers, standards, eBooks, and eLearning courses.

Learn more about:

IEEE membership

IEEE Xplore subscriptions

3 Author(s)
W. Aloisi ; Dipt. di Ingegneria Elettrica Elettronica e dei Sistemi, Univ. Degli Studi di Catania, Italy ; G. Giustolisi ; G. Palumbo

This paper investigates the design of low-voltage low-power switched-capacitor (SC) filters for high-frequency applications by using the clock-booster approach. In particular, our proposed SC filter architecture uses single-ended double-sampling integrator cells based on low-voltage operational transconductance amplifiers which take advantage of dynamic biasing and the clock-booster technique to drive the switch transistors. To validate its high-frequency capability, two low-pass elliptic SC filters respectively with a corner frequency of 6 and 8-MHz, were designed in a 0.35-μm CMOS process. Both are suitable for telecom applications and can operate with a power supply as low as 1.5 V, while dissipating 11 mW. Measurements showed that for an output amplitude of 1 Vpp, their total harmonic distortions were maintained well below -40 dB in their bandwidths. Comparisons with other SC filter implementations in the literature, which highlight the quality of our implementation are also provided.

Published in:

IEEE Transactions on Circuits and Systems II: Express Briefs  (Volume:51 ,  Issue: 2 )