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Fast convergent pipelined adaptive DFE architecture using post-cursor processing filter technique

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3 Author(s)
Meng-Da Yang ; Dept. of Electr. Eng., Nat. Taiwan Univ., Taipei, Taiwan ; An-Yeu Wu ; Jyh-Ting Lai

Among existing works of high-speed pipelined adaptive decision feedback equalizers (ADFE), the pipelined ADFE using relaxed look-ahead technique results in a substantial hardware saving than the parallel processing or other look-ahead approaches. For example, Shanbhag and Partiz derived three pipeline ADFE structures (PIPEADFE1, 2, 3), where PIPEADFE2 yields very good performance in terms of convergence rate and hardware cost. Nevertheless, the PIPEADFE2 employs Approximation Methods in deriving the Preprocessing Unit (PP). In this paper, a new pipelining ADFE architecture is developed. We derive a new updating ADFE scheme based on the Principle of Orthogonality. By employing the postcursor processing filter (PCF) to cancel the most significant postcursor Intersymbol interference (ISI) terms, the proposed PCFADFE architecture can significantly improve the convergence rate of the ADFE. Compared with PIPEADFE2, it has better convergence rate while at similar hardware cost. Hence, it provides an alternative approach for the design of high-speed pipelining ADFE with arbitrary speedup factor.

Published in:

Circuits and Systems II: Express Briefs, IEEE Transactions on  (Volume:51 ,  Issue: 2 )

Date of Publication:

Feb 2004

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