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Design, analysis, and implementation of DVSR: a fair high-performance protocol for packet rings

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6 Author(s)
Gambiroza, V. ; Electr. & Comput. Dept., Rice Univ., Houston, TX, USA ; Ping Yuan ; Balzano, L. ; Yonghe Liu
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The Resilient Packet Ring (RPR) IEEE 802.17 standard is a new technology for high-speed backbone metropolitan area networks. A key performance objective of RPR is to simultaneously achieve high utilization, spatial reuse, and fairness, an objective not achieved by current technologies such as SONET and Gigabit Ethernet nor by legacy ring technologies such as FDDI. The core technical challenge for RPR is the design of a bandwidth allocation algorithm that dynamically achieves these three properties. The difficulty is in the distributed nature of the problem, that upstream ring nodes must inject traffic at a rate according to congestion and fairness criteria downstream. Unfortunately, we show that under unbalanced and constant-rate traffic inputs, the RPR fairness algorithm suffers from severe and permanent oscillations spanning nearly the entire range of the link capacity. Such oscillations hinder spatial reuse, decrease throughput, and increase delay jitter. In this paper, we introduce a new dynamic bandwidth allocation algorithm called Distributed Virtual-time Scheduling in Rings (DVSR). The key idea is for nodes to compute a simple lower bound of temporally and spatially aggregated virtual time using per-ingress counters of packet (byte) arrivals. We show that with this information propagated along the ring, each node can remotely approximate the ideal fair rate for its own traffic at each downstream link. Hence, DVSR flows rapidly converge to their ring-wide fair rates while maximizing spatial reuse. To evaluate DVSR, we develop an idealized fairness reference model and bound the deviation in service between DVSR and the reference model, thereby bounding the unfairness. With simulations, we find that compared to current techniques, DVSR's convergence times are an order of magnitude faster (e.g., 2 versus 50 ms), oscillations are mitigated (e.g., ranges of 0.1% versus up to 100%), and nearly complete spatial reuse is achieved (e.g., 0.1% throughput loss versus 33%). Finally, we provide a proof-of-concept implementation of DVSR on a 1 Gb/s network processor testbed and report the results of testbed measurements.

Published in:

Networking, IEEE/ACM Transactions on  (Volume:12 ,  Issue: 1 )

Date of Publication:

Feb. 2004

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