A delay spread based low power reconfigurable FFT processor architecture for wireless receiver

This paper proposes a novel concept of adjusting the FFT size in real time as per the delay spread in wireless receivers. The FFT size in OFDM/MC-CDMA based wireless receivers varies from 1024(1k)-point to 16-point. A low power reconfigurable radix-4 1k-point FFT processor architecture is proposed that can also be configured as a 256-point, 64-point or 16-point as per the channel parameters. By tailoring the clock of the higher FFT stages for longer FFT's, significant power saving is achieved by switching to shorter FFTs from longer FFTs.