Cart (Loading....) | Create Account
Close category search window
 

CTL based DFT solution to accelerate design to test development for system on chip devices

Sign In

Cookies must be enabled to login.After enabling cookies , please use refresh or reload or ctrl+f5 on the browser for the login options.

Formats Non-Member Member
$31 $13
Learn how you can qualify for the best price for this item!
Become an IEEE Member or Subscribe to
IEEE Xplore for exclusive pricing!
close button

puzzle piece

IEEE membership options for an individual and IEEE Xplore subscriptions for an organization offer the most affordable access to essential journal articles, conference papers, standards, eBooks, and eLearning courses.

Learn more about:

IEEE membership

IEEE Xplore subscriptions

1 Author(s)

In this presentation, we will explain how CTL has been designed as a very rich and powerful language that can be leveraged in a DFT solution. While CTL has been designed with the primary focus of communicating information between the core providers and the SoC test integrators, it is showing very useful as a communication mechanism form the EDA world to the ATE. CTL does not only support cores tested with the standard scan approach; IP blocks with embedded logic BIST and memories can also be described in CTL. An EDA DFT solution based on CTL enables full automation of scan and BIST at the core level and test integration at the SoC level.

Published in:

System-on-Chip, 2003. Proceedings. International Symposium on

Date of Conference:

19-21 Nov. 2003

Need Help?


IEEE Advancing Technology for Humanity About IEEE Xplore | Contact | Help | Terms of Use | Nondiscrimination Policy | Site Map | Privacy & Opting Out of Cookies

A not-for-profit organization, IEEE is the world's largest professional association for the advancement of technology.
© Copyright 2014 IEEE - All rights reserved. Use of this web site signifies your agreement to the terms and conditions.