A guaranteed-throughput switch for network-on-chip

Today's systems on a chip (SoC) contain numerous complex functional blocks integrated by an elaborate network of interconnects and buses. As systems grow in complexity, the on-chip interconnect network is expected to become critical for overall system-level metrics, such as performance, power consumption, reliability etc. However, present day's dedicated channels and shared buses do not scale and therefore do not meet these requirements. The emerging network-on-chip approach, based on on-chip communication network, might solve the problems by A. Jantsch and H. Tenhunen (2003). In this paper, a guaranteed-throughput switch designed for NoC is described. This switch provides in-order delivery and supports multicast operation. It is implemented with random access memory at the input and output. The input and output are then connected by a fully connected interconnect network.