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Modified register-exchange Viterbi decoder for low-power wireless communications

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2 Author(s)
El-Dib, D.A. ; VLSI Res. Group, Univ. of Waterloo, Ont., Canada ; Elmasry, M.I.

In this paper, a new implementation of the Viterbi decoder (VD), based on a modified register-exchange (RE) method, is proposed. Conceptually, the RE method is simpler and faster than the trace-back (TB) method. However, the disadvantage of the RE method is that every bit in the memory must be read and rewritten for each bit of information decoded. The proposed implementation adopts the "pointer" concept: a pointer is assigned to each register. Instead of copying the contents of one register to another, the pointer which points to the first register is altered to point to the second register. Power-dissipation, performance, memory size, and the speed of the survivor sequence management are analyzed for both the TB method, and the proposed RE method. The analysis indicates an average power reduction of 23% for the new VD, compared to the power dissipation of the VD described in the literature for the third generation of wireless applications. The bit-error rate is 10-5 with a signal-to-noise ratio of approximately 6.3 dB for a continuous, uncontrolled encoded sequence. Moreover, the memory requirements of the new implementation are reduced by half. All the read and write operations in the survivor sequence management are executed at the data rate frequency which increases the maximum frequency.

Published in:

Circuits and Systems I: Regular Papers, IEEE Transactions on  (Volume:51 ,  Issue: 2 )

Date of Publication:

Feb. 2004

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