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RapidIO™ is a pseudo-serial, source-synchronous, point-to-point interconnect which enables reliable, high-speed intra-system communication. The RapidIO physical layer utilises low-voltage differential signaling (LVDS) pairs that interconnect RapidIO link partners belonging to end-points or central switch fabrics. The following is an investigation into the performance of the RapidIO architecture when deployed as the interconnection between the components of a generic switch device. A discrete event simulation model of such a system has been developed enabling various compositions of traffic to be offered to the device. Extensive simulations have enabled a quantitative analysis of various performance metrics that indicate how the device deals with various classes of traffic under saturating and non-saturating aggregate traffic loads. The results therefore provide an insight into the general performance capabilities of the RapidIO architecture as a transport protocol as well as outlining some specific issues regarding implementing RapidIO to interconnect components of a generic switch device.