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Characterization of spatial intrafield gate CD variability, its impact on circuit performance, and spatial mask-level correction

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3 Author(s)
M. Orshansky ; Dept. of Electr. & Comput. Eng., Univ. of Texas, Austin, TX, USA ; L. Milor ; Chenming Hu

The authors present a comprehensive characterization method applied to the study of the state-of-the-art 18-μm CMOS process. Statistical characterization of gate CD reveals a large spatial intrafield component, strongly dependent on the local layout patterns. The authors describe the statistical analysis of this data and demonstrate the need for such comprehensive characterization. They describe the experimental setup of the novel measurement-based characterization approach that is capable of capturing all the relevant CD variation patterns necessary for accurate circuit modeling and statistical design for increased performance and yield. Characterization is based upon an inexpensive electrically based measurement technique. A rigorous statistical analysis of the impact of intrafield variability on circuit performance is undertaken. They show that intrafield CD variation has a significant detrimental effect on the overall circuit performance that may be as high as 25%. Moreover, they demonstrate that the spatial component of gate CD variability, rather than the proximity-dependent component, is predominantly responsible for speed degradation. In order to reduce the degradation of circuit performance and yield, the authors propose a mask-level spatial gate CD correction algorithm to reduce the intrafield and overall variability and provide an analytical model to evaluate the effectiveness of correction for variance reduction. They believe that potentially significant benefits can be achieved through implementation of this compensation technique in the production environment.

Published in:

IEEE Transactions on Semiconductor Manufacturing  (Volume:17 ,  Issue: 1 )