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A high-speed sensing scheme for 1T dynamic RAMs utilizing the clamped bit-line sense amplifier

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2 Author(s)
T. N. Blalock ; Dept. of Electr. Eng., Auburn Univ., AL, USA ; R. C. Jaeger

A clamped-bit-line sense amplifier (CBLSA) capable of very high-speed operation in one-transistor (1T) DRAM applications has been developed. Results from an experimental test chip demonstrate that the speed of the new circuit is insensitive to bit-line capacitance. Circuit speed is also found to be insensitive to the initial bit-line difference voltage. The CBLSA maintains a low impedance fixed potential on the bit lines during sensing, virtually eliminating sensitivity to inter-bit-line noise coupling and minimizing power supply bounce during sensing. The new sense amplifier operates at higher speeds than conventional circuits and still dissipates less power

Published in:

IEEE Journal of Solid-State Circuits  (Volume:27 ,  Issue: 4 )