Deep-submicrometer BiCMOS circuit technology for sub-10-ns ECL 4-Mb DRAM's

A 0.3- mu m sub-10-ns ECL 4-Mb BiCMOS DRAM design is described. The results obtained are: (1) a V/sub cc/ connection limiter with a BiCMOS output circuit is chosen due to ease of design, excellent device reliability and layout area; (2) a mostly CMOS periphery with a specific bipolar use provides better performances at high speed and low power; (3) the direct sensing scheme of a single-stage MOS preamplifier combined with a bipolar main amplifier offers high speed; and (4) the strict control of MOS transistor parameters has been proven to be more important in obtaining high speed DRAMs, based on the 4-Mb design.<
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