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Fault-tolerant architecture in a cache memory control LSI

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4 Author(s)
Ooi, Y. ; NEC Corp., Kanagawa, Japan ; Kashimura, M. ; Takeuchi, H. ; Kawamura, E.

A real-time degradable four-way set-associative cache memory control (CMC) LSI is described. Three kinds of errors, address parity error, comparator error, and multihit error, can cause functional degradation by killing the associative unit corresponding to the fault detection. The parity generator and the double comparator have no effect on the timing-sensitive path delay because of the parallel configuration of the circuits. The multihit detector occupies about 16% of the propagation delay of the critical path, from the external address input to the hit/miss output

Published in:

Solid-State Circuits, IEEE Journal of  (Volume:27 ,  Issue: 4 )

Date of Publication:

Apr 1992

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