By Topic

Optimization of extrinsic source/drain resistance in ultrathin body double-gate FETs

Sign In

Cookies must be enabled to login.After enabling cookies , please use refresh or reload or ctrl+f5 on the browser for the login options.

Formats Non-Member Member
$31 $13
Learn how you can qualify for the best price for this item!
Become an IEEE Member or Subscribe to
IEEE Xplore for exclusive pricing!
close button

puzzle piece

IEEE membership options for an individual and IEEE Xplore subscriptions for an organization offer the most affordable access to essential journal articles, conference papers, standards, eBooks, and eLearning courses.

Learn more about:

IEEE membership

IEEE Xplore subscriptions

2 Author(s)
Shenoy, R.S. ; Dept. of Electr. Eng., Stanford Univ., CA, USA ; Saraswat, K.C.

Extrinsic resistance due to contacts and nonabrupt lateral extension doping profile can become a performance-limiter in ultrathin body double-gate FETs (DGFET). In this paper, two-dimensional device simulations are used to study and optimize the extrinsic resistance in a sub-20 nm gate length DGFET. For a given lateral doping gradient, the extension doping needs to be offset from the gate edge by an amount called the underlap. The current drive, and hence transistor performance, is maximized when the underlap is chosen in such a way as to balance the impact of nonabrupt doping on the short channel effects and series resistance. This optimization depends upon the maximum allowed off-state subthreshold leakage current and the electrostatic integrity of the device structure.

Published in:

Nanotechnology, IEEE Transactions on  (Volume:2 ,  Issue: 4 )