Referenced Items are not available for this document.
A 10 Gbit/s timing recovery circuit using GaAs IC technology is presented. A jitter suppression method using two cascaded differentiators is proposed. The phase deviation characteristics of a timing recovery circuit for mark density variation are also discussed.
Published in:
Electronics Letters
(Volume:28
,
Issue:
4
)
Date of Publication: 13 Feb. 1992
- Page(s):
- 403 - 405
- ISSN :
- 0013-5194
- INSPEC Accession Number:
- 4122675
- Digital Object Identifier :
- 10.1049/el:19920253
- Product Type:
- Journals & Magazines
- Date of Current Version :
- 06 August 2002
- Issue Date :
- 13 Feb. 1992
- Sponsored by :
- Institution of Engineering and Technology
About IEEE Xplore | Contact | Help | Terms of Use | Nondiscrimination Policy | Site Map | Privacy & Opting Out of Cookies
A not-for-profit organization, IEEE is the world's largest professional association for the advancement of technology.
© Copyright 2013 IEEE - All rights reserved. Use of this web site signifies your agreement to the terms and conditions.
