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Identification and classification of single-event upsets in the configuration memory of SRAM-based FPGAs

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10 Author(s)
M. Ceschia ; Dipt. di Ingegneria dell'Informazione, Univ. di Padova, Italy ; M. Violante ; M. S. Reorda ; A. Paccagnella
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This paper presents the radiation testing of a commercial-off-the-shelf SRAM-based field-programmable gate arrays (FPGAs) with heavy ions. Test experiments have been conducted to identify and to classify the single-event upsets (SEUs) in the configuration memory that induce single-event functional interrupt for the user-implemented circuit. Moreover the paper presents a new approach for assessing the effects of SEUs based on the combination of radiation testing and simulation-based fault injection tool. First experimental results show the FPGA look-up table (LUT) resources (used to implement combinatorial logic) are the most sensitive to SEUs, whereas interconnect resources are the most critical for the device cross section because they use the largest number of configuration bits. The analysis of experimental data underlines that the most probable error affecting interconnections is the shorting of two nets. This observation indicates that new fault models should be considered along with the classic stuck-at one model designing fault-tolerant architectures, which are intended for implementation in FPGA devices.

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IEEE Transactions on Nuclear Science  (Volume:50 ,  Issue: 6 )