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Computation sharing programmable FIR filter for low-power and high-performance applications

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6 Author(s)
Jongsun Park ; Sch. of Electr. & Comput. Eng., Purdue Univ., West Lafayette, IN, USA ; Jeong, W. ; Mahmoodi-Meimand, H. ; Yongtao Wang
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This paper presents a programmable digital finite-impulse response (FIR) filter for high-performance and low-power applications. The architecture is based on a computation sharing multiplier (CSHM) which specifically targets computation re-use in vector-scalar products and can be effectively used in the low-complexity programmable FIR filter design. Efficient circuit-level techniques, namely a new carry-select adder and conditional capture flip-flop (CCFF), are also used to further improve power and performance. A 10-tap programmable FIR filter was implemented and fabricated in CMOS 0.25-μm technology based on the proposed architectural and circuit-level techniques. The chip's core contains approximately 130 K transistors and occupies 9.93 mm2 area.

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Solid-State Circuits, IEEE Journal of  (Volume:39 ,  Issue: 2 )