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Jitter characterization has become significantly more important for systems running at multigigahertz data rates. Time and frequency domain characterization of jitter is thus a crucial element for system specification testing. Time domain jitter measurement on a data signal with subgate timing resolution can be achieved using two delay chains feeding into the clock and datalines of a series of D-latches known as a Vernier delay line (VDL). An important drawback to the VDL structure is that its measurement accuracy depends on the matching of the various delay elements. Although careful layout techniques can help to minimize these mismatches, it cannot eliminate them completely. As well, due to the nature of the design, a relatively large silicon area is required for silicon implementation. In this paper, a novel technique is developed which reduces the silicon area requirements by two orders of magnitude, as well enables the measurement device to be synthesized from a register transfer level (RTL) description. A custom IC was designed and fabricated in a 0.18-/spl mu/m CMOS process as a first proof of concept. The design requires a silicon area of 0.12 mm/sup 2/ and measured results indicate a timing resolution of 19 ps. The synthesizable nature of the design is demonstrated using an field-programmable gate-array implementation. As test time is an important consideration for a production test, an extension to the component-invariant VDL technique is provided that reduces test time at the expense of more hardware. Finally, a method for obtaining the frequency domain characteristics of the jitter using the VDL will also be given.