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Linearization of the timing analysis and optimization of level-sensitive digital synchronous circuits

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2 Author(s)
Taskin, B. ; Dept. of Electr. Eng., Univ. of Pittsburgh, PA, USA ; Kourtev, I.S.

This paper describes a linear programming (LP) problem formulation applicable to the static-timing analysis of large scale synchronous circuits with level-sensitive latches. Specifically, an LP formulation for the clock period minimization problem is developed. In order to minimize the clock period of level-sensitive circuits, the simultaneous effects of time borrowing and nonzero clock skew scheduling are considered. The clock period minimization problem is formulated for both single-phase and multi-phase clocking schemes. The ISCAS'89 benchmark circuits are used to derive experimental results. LP minimization problems for these benchmark circuits are generated using the modified big M (MBM) method and the generated problems are solved using the industrial LP solver CPLEX . The experimental results demonstrate up to 63% improvements in minimum clock period compared to flip-flop based circuits with zero clock skew.

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Very Large Scale Integration (VLSI) Systems, IEEE Transactions on  (Volume:12 ,  Issue: 1 )