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A distributed shared memory multiprocessor: ASURA - Memory and cache architectures

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9 Author(s)
S. -I. Mori ; Dept. of Inf. Sci., Kyoto Univ., Japan ; H. Saito ; M. Goshima ; M. Yanagihara
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ASURA is a large scale, cluster-based, distributed, shared memory, multiprocessor being developed at Kyoto University and Kubota Corporation. Up to 128 clusters are interconnected to form an ASURA system of up to 1024 processors. The basic concept of the ASURA design is to take advantage of the hierarchical structure of the system. Implementing this concept, a large shared cache is placed between each cluster and the inter-cluster network. The shared cache and the shared memories distributed among the clusters form part of ASURA's hierarchical memory architecture, providing various unique features to ASURA. In this paper, the hierarchical memory architecture of ASURA and its unique cache coherence scheme, including a proposal of a new hierarchical directory scheme, are described with some simulation results.

Published in:

Supercomputing '93. Proceedings

Date of Conference:

15-19 Nov. 1993