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Fast context switching by hierarchical task allocation and reconfigurable cache

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1 Author(s)
Tanaka, K. ; Sch. of Inf. Sci., Japan Adv. Inst. of Sci. & Technol., Ishikawa, Japan

A multithreaded processor architecture enables fast context switching for tolerating memory access latency and bridging synchronization gap, and thus enables efficient utilization of execution pipelines. However, it cannot prevent all pipeline stalls; stalls will still occur when all processor built-in threads are in a wait state or there are not enough threads in a task to fill up all available context slots, since the mechanism for switching active threads is effective only for processor built-in contexts. In this paper, we propose an architecture that increases the virtual number of built-in contexts and enables seamless task switching by allocating and swapping task contexts hierarchically between processor and memory in a multitasking environment. At the same time, we aim at supporting real-time applications through hierarchical task allocation based on task priority and fast response mechanisms for interrupt requests exploiting the multiple-context architecture. Moreover, we propose two reconfigurable cache applications, a priority-based partitioning cache and a FIFO buffer, and their implementation methods. We have extended the general-purpose RISC processor architecture and are developing a new RISC core which can be used to implement the seamless task switching, fast response to interrupt requests, and the reconfigurable caches, for supporting real-time processing in a multi-tasking environment. we describe the design of the RISC core in this paper.

Published in:

Innovative Architecture for Future Generation High-Performance Processors and Systems, 2003

Date of Conference:

17 July 2003