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A low-noise amplifier (LNA) implemented in a low-cost Si-BiCMOS 0.8-μm process is presented. It utilizes current conveyors as building blocks. The principle and design methodology are presented, followed by results obtained from simulations. A brief technology and measurement technique description is then made, leading up to the measurement results obtained. The performance is compared with some other LNA realizations. The potentialities of the LNA are finally touched upon, with particular regard to future communications systems. The gain of the LNA is controllable, in the range of 0-20 dB, by varying the dc bias current. Negative decibel gains can also be obtained, making it an attenuator circuit. Using a ±1.5 V supply, and at a measured gain of 14 dB, the LNA has measured -3 dB bandwidth of dc to 1.9 GHz, |ZIN| = 50 Ω, |S11| = -21 dB, and a simulated noise figure = 3.3 dB, input P1dB = -33 dBm, and consumes only 3.8 mA. A judicious tradeoff between the decibel gain and bandwidth yields -3 dB bandwidths of up to 5.5 GHz, while in the -10-dB cutoff specified for ultra-wide-band (UWB) systems, passbands greater than 10 GHz are enabled. The LNA occupies 0.24 mm2 of chip area, including pads. The prospective applications range from current global system for mobile communications, code division multiple access, and multiband systems, to the upcoming UWB.