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Bias polarity dependent effects of P+floating gate EEPROMs

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3 Author(s)
Kuo, C. ; Dept. of Electr. Eng. & Comput. Sci., Univ. of California, Berkeley, CA, USA ; Tsu-Jae King ; Chenming Hu

EEPROM devices with either N-type or P-type floating gate were fabricated and characterized. Program/erase speeds and stress-induced leakage current-related retention characteristics for both types of devices are explained. Discrepancies between previously published reports on P-type floating gate devices and PMOS gate current measurements are resolved. The feasibility of integrating P-type floating gate EEPROMs in high density memory arrays is examined.

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Electron Devices, IEEE Transactions on  (Volume:51 ,  Issue: 2 )